Job Responsibilities

1. Participate in the development, logic design, and verification of flash memory chips, focusing on logic block implementation and chip-level validation.

2. Define design specifications based on customer functional requirements.

3. Develop module-level Verilog/SystemVerilog models and perform firmware-level coding.

4. Build mixed-signal simulation environments and integrated chip-level test platforms.

5. Develop verification scripts and test programs according to design requirements.

6. Support debugging of chip-level functional and test issues.

Qualifications

1. Bachelor’s degree or above in Microelectronics or related disciplines; candidates with semiconductor design coursework are also welcome.

2. Familiarity with the digital design flow; able to independently complete RTL coding and simulation in front-end design.

3. Proficiency in RTL coding, Verilog simulation, and synthesis tools is preferred.

4. Understanding of full-custom IC design flow and experience with Cadence Virtuoso is a plus.

5. Strong English communication skills, both written and verbal.

6. Honest, diligent, responsible, and capable of working under pressure.

7. Strong analytical thinking, learning agility, communication skills, and a team-oriented mindset.

Job Responsibilities

1. Design and simulate analog circuits for integrated chips.

2. Responsible for data path and I/O circuit design.

3. Guide layout engineers on floorplanning, performance optimization, and module size tuning.

4. Design and verify test-related circuitry based on process and silicon validation requirements.

5. Support chip testing and post-silicon debugging.

Qualifications

1. Bachelor’s degree or above in Microelectronics or related fields; candidates with semiconductor design course experience are also welcome.

2. Proficient in simulation tools such as HSPICE and NanoSim.

3. Experience with ADC, DAC, LDO, PUM, or I/O circuit design is a strong plus.

4. Strong written and spoken English skills.

5. High integrity, strong work ethic, sense of responsibility, and ability to work under pressure.

6. Strong learning ability, problem-solving skills, communication, and team spirit.

Job Responsibilities

1. Interpret chip and module-level design requirements and complete overall layout planning.

2. Perform layout design for both block-level and top-level modules according to design rules and circuit constraints.

3. Conduct layout verification including LVS, DRC, ANTENNA, PERC, and other physical checks.

4. Generate layout deliverables such as Abstract and LEF files.

5. Extract parasitic parameters and support circuit engineers in post-layout simulation.

6. Assist APR (Automatic Place and Route) engineers in SoC-level chip integration.

7. Prepare tape-out-related data and documentation.

8. Write and maintain technical documents related to layout design.

Qualifications

1. Bachelor’s degree or above in Microelectronics, Electrical Engineering, or related fields; candidates with coursework in semiconductor design are also encouraged to apply.

2. Solid understanding of the IC design flow, with basic knowledge of semiconductor devices and analog circuit principles.

3. Proficiency in IC layout design and verification tools such as Cadence and Calibre is preferred.

4. Experience with Virtuoso-XL is a strong plus.

5. Prior experience in memory layout (Flash, SRAM, ROM, etc.) is advantageous.

6. Familiarity with SKILL, TCL, and experience in APR is preferred.

7. Strong written and verbal communication skills in English.

8. Honest, responsible, self-motivated, with the ability to work under pressure.

9. Demonstrated strengths in learning, problem-solving, communication, and team collaboration.

Job Responsibilities:

Validate user guides and test functions for memory products; define test procedures, develop test programs, improve coverage, and optimize test time.

• Define product test modes, including BIST, DFT, and DFM strategies.

• Conduct failure analysis using electrical fault testing, circuit-level diagnostics, physical analysis, and data interpretation to identify root causes of wafer-level failures post-fabrication.

• Collaborate with product design and process engineering teams to identify and resolve the root causes of product failures.

• Perform additional tasks as assigned by direct supervisors or team leads.

Qualifications

• Bachelor’s degree or above in Microelectronics, Semiconductor Materials, or related fields.

• 10+ years of experience in CP test platform development.

• Programming experience in C/C++/Python; experience with ATE platforms such as T5830, T5833, Magnum, or V93k is highly preferred.

• Strong understanding of semiconductor product principles and testing mechanisms; familiar with the functional, performance, and reliability specifications of memory devices.

• Background in memory design verification (including but not limited to NOR/NAND flash) is preferred.

Job Responsibilities

• Design and verify high-speed data path modules for DDR interfaces and pipelined architectures within NAND or DRAM memory systems.

• Perform high-precision modeling and circuit simulation; correlate with post-silicon performance data.

• Guide layout engineers in improving layout planning and enhancing layout performance.

• Support product test engineers in post-silicon validation and debugging activities.

Qualifications

• Bachelor’s degree or above in Electrical Engineering or related disciplines, with experience in circuit design.

• Strong foundation in analog and mixed-signal circuit design.

• Proficient in EDA tools such as Virtuoso, HSPICE, FineSim, etc.

• Proactive, with strong communication and collaboration skills.

• Experience in memory, flash, or high-speed I/O design is a plus.

• Knowledge of ESD protection, IC packaging, or RTL is preferred.